1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection circuits, and more particularly to a programming pad ESD protection circuit.
2. Description of the Prior Art
Flash memory is a type of non-volatile memory commonly employed in memory cards, flash drives, and portable electronics for providing data storage and transfer. Flash memory may be electrically written to, erased, and reprogrammed to allow deletion of data and writing of new data. Some advantages of flash memory include fast read access time, and shock resistance. Flash memory is also very resistant to pressure and temperature variations.
Please refer to FIG. 1, which is a diagram of a protection circuit 101 and a core circuit 100 according to the prior art. The core circuit 101 comprises a transistor T2, and the protection circuit 101 is electrically connected to a gate electrode of the transistor T2. The protection circuit 101 comprises a transistor T5 having a drain electrode electrically connected to the gate electrode of the transistor T2, a source electrode electrically connected to ground, and a gate electrode electrically coupled to an input node IN through a capacitor C1. The drain electrode of the transistor T5 is electrically coupled to the input node IN through a resistor R1. A resistor R2 is coupled between the gate electrode of the transistor T5 and ground. A capacitor C2 is a parasitic gate-ground capacitor of the transistor T5. When a high voltage is applied to the input node IN, the capacitors C1, C2 divide the voltage, turning the transistor T5 on. Thus, voltage that would be applied to the gate electrode of the transistor T2 is sunk to ground through the transistor T5, thereby protecting the gate electrode of the transistor T2.
Please refer to FIG. 2, which is a diagram of a flash memory circuit 20 according to the prior art. The flash memory circuit 20 includes a plurality of flash memory blocks 200 that are programmable through a programming voltage VPP applied at a pad VPP_PAD. A gate driven circuit 210 drives a gate electrode of a pass gate 230 to allow the programming voltage VPP to be sent to the flash memory blocks 200. The pass gate 230 comprises an N-type metal-oxide semiconductor (NMOS) transistor N3 and a P-type metal-oxide-semiconductor (PMOS) transistor P0. A gate electrode of the NMOS transistor N3 is electrically connected to a node G2; a gate electrode of the PMOS transistor P0 is electrically connected to a node G1. When the programming voltage VPP is applied at the pad VPP_PAD, voltage at the node G2 increases to approximately the programming voltage VPP, and voltage at the node G1 is pulled down by an NMOS transistor N1, which is turned on. Thus, the pass gate 230 turns on, and the programming voltage VPP may be sent to the flash memory blocks 200. If no voltage is applied at the pad VPP_PAD, e.g. the pad VPP_PAD is grounded, voltage at the node G2 decreases to approximately ground, turning off the NMOS transistor N1, and thereby turning off the pass gate 230, effectively cutting off voltage applied to the pad VPP_PAD from the flash memory blocks 200. Programming may occur when the programming voltage VPP is high, or when the programming voltage VPP is low, e.g. 0V. In other words, the programming voltage VPP may operate as a high voltage or a low voltage.
Electrostatic discharge (ESD) entering the flash memory circuit 20 through the pad VPP_PAD is one potential source of damage to the flash memory blocks 200. To mitigate the ESD effect, one goal is to direct excess charges to a lower potential node, such as ground. The flash memory circuit 20 thus further comprises an ESD transistor N0 for redirecting ESD current away from the flash memory blocks 200. When the voltage applied to the pad VPP_PAD goes high, a gate electrode of the ESD transistor N0 is temporarily pulled high at the node G1 through the PMOS transistor P1, because a capacitor C1 and a resistor R0 keep gates of the NMOS transistor N1 and the PMOS transistor P1 low while the capacitor C1 is charged by the ESD charges. ESD zapping typically occurs for a period on the order of nanoseconds. Thus, the resistor R0 and the capacitor C1 may be designed with a RC time constant of approximately 1 us to keep the ESD transistor N0 turned on long enough to redirect most or all of the ESD current.
One problem that may occur in either of the circuits described above is accidental programming of one of the flash memory blocks during the ESD zapping event.